1. Field of the Invention
The embodiment relates to a printed circuit board, a package substrate, and a method of fabricating the same.
2. Description of Related Art
In general, the package substrate has a structure in which a first substrate having a memory chip attached thereto is integrated with a second substrate having a processor chip attached thereto.
The package substrate has advantages in that the mounting area of the chips can be reduced, and a signal can be transmitted at a high rate as the processor chip and the memory chip are integrated in one package.
The package substrate has been extensively applied to various mobile appliances due to the advantages.
FIG. 1 is a sectional view showing a package substrate according to the related art.
Referring to FIG. 1, the package substrate includes a first substrate 20 and a second substrate 30 attached onto the first substrate 20.
In addition, the first substrate 20 includes a first insulating layer 1, a circuit pattern 2 formed on at least one surface of the first insulating layer 1, a second insulating layer 2 formed on the first insulating layer 1, a third insulating layer 3 formed under the first insulating layer 1, a circuit pattern 4 formed on at least one surface of the first insulating layer 1, a conductive via 5 formed in at least one of the second insulating layer 2 and the third insulating layer 3, a pad 6 formed on a top surface of the second insulating layer 2, a plurality of bonding pastes 7 formed on the pad 6, a memory chip 8 formed on at least one of the bonding pastes 7, a first protective layer 10 formed on the second insulating layer 2 to expose a portion of a top surface of the pad 6 and a second protective layer 9 formed on the protective layer 10 to cover the memory chip 8.
In addition, the second substrate 30 includes a fourth insulating layer 11, a circuit pattern 12 formed on at least one surface of the fourth insulating layer 11, a pad 13 formed on at least one surface of the fourth insulating layer 11, a conductive via 14 formed in at least one surface of the fourth insulating layer 11, a processor chip 15 formed on the fourth insulating layer 11, and a connection member S to connect the processor chip 15 with the pad 13.
FIG. 1 is a schematic view showing a package on package (PoP) employing a through mold via (TMV) technology based on a laser technology.
According to the TMV technology, after molding the first substrate, a conductive via to be connected with the pad is formed through a laser process, so that a solder ball (bonding paste) is printed in the conductive via.
In addition, the second substrate 30 is attached to the first substrate 20 by the printed solder ball 7.
However, the related art has a limitation in forming a fine pitch since the first substrate is connected with the second substrate using the solder ball 7.
In addition, according to the related art, since the solder ball 7 is used, issues such as a solder crack, a solder bridge, and a solder collapse, may be occur.